In order to facilitate the testing of silicon devices such as processors while using Debug, Validation, and Coverage Analysis (for example, Probe less Debug Methodology, otherwise known as PDM), the inventors have contemplated using micro-code patches to capture information and send it to a post-silicon debug tool such as an In Target Probe (ITP). However, several patched events are desirable to be captured for Debug, Validation, and Coverage Analysis, and for devices with limited micro-code patch memory space it is not possible to fit all of the patch flows into the patch memory. Additionally, limited patch space continues to increase as an issue as patches are becoming more and more complex and as the number of events to be captured continues to increase.
Methodologies which enable traces to be taken and merged across multiple, repeatable execution passes do not provide sufficient coverage for all Debug and Validation needs. In many environments macro-level execution repeatability cannot be guaranteed. There is also a need to load patches very quickly, so that execution performance does not become unreasonably slow.